Computer architecture, pipeline concept, CPU internal structure, data flow diagram, instruction fetch, decode, execute, memory access, write back, register renaming, Tomasulo's algorithm, out-of-order execution, in-order completion, hazard detection, forwarding, stall, flush, RISC/CISC architectures, cache hierarchy, superscalar, speculative execution, branch prediction, resolution, latency hiding, throughput optimization, digital circuitry, microarchitecture, gate-level implementation, clock cycle, frequency domain analysis, instruction-level parallelism.