DMA controller, modern architecture, CPU-centric design, peripherals connected via bus, burst mode operation, single-cycle transfer, flow control mechanism, data transfer between devices, memory-mapped I/O, asynchronous operation, interrupt-driven processing, scatter-gather operations, data alignment rules, byte lane shifting, beat tracking, write allocation, read prefetching, cache coherence protocol, system interconnect, multi-layer AMBA bus, priority arbitration logic, transaction routing, response signaling, power management unit, low-power mode, clock domain crossing, asynchronous clock bridge, pipelined data transfer engine.