CPU architecture, block diagram, complex integrated circuit, central processing unit, ALU, arithmetic logic unit, registers, cache memory, main memory, bus interface, instruction decoder, execution units, load-store units, branch prediction, pipelining, superscalar, out-of-order execution, register renaming, speculative execution, Tomasulo's algorithm, scoreboard, reorder buffer, reservation station, ROB, load latency, store latency, misaligned data, page table walk, virtual address space, physical address space, memory management unit, TLB, translation lookaside buffer, cache coherence protocol, MESI protocol, snooping, write invalidate, write update, read for ownership, directory-based protocol, hierarchical bus architecture, point-to-point interconnects, packet-switching interconnects, network-on-chip, 3D stacked architecture, thermal design power gating, clock domain crossing, voltage-frequency island, dynamic voltage and frequency scaling, power management unit, sleep mode, idle mode, shutdown mode, wake-up latency, context switch, thread-level parallelism, simultaneous multithreading, coarse-grained multithreading, fine-grained multithreading, hardware thread scheduling, cache-aware thread scheduling, thread migration, resource allocation, quality of service, real-time computing, low-latency interrupt handling, deferred interrupt handling, interrupt coalescing, interrupt nesting, priority encoding, interrupt latency hiding.