Design, 16-bit, ISA, instruction set architecture, processor, microprocessor, computer chip, electronic circuit, motherboard, CPU, central processing unit, RISC, reduced instruction set computing, Harvard architecture, pipelining, 16 registers, 8 general-purpose registers, 4 segment registers, 2 index registers, 1 program counter register, 1 stack pointer register, load-store architecture, 3-operand instructions, fixed-length 16-bit instructions, big-endian byte order, little-endian word order, instruction encoding, opcode, operand, immediate value, memory addressing modes, direct, indirect, indexed, stack-based, arithmetic logic unit, ALU, shifter, multiplier, divider, flags register, conditional branch instructions, unconditional jump instructions, subroutine call and return instructions, interrupt handling, exception handling, system calls, user mode, kernel mode, privilege levels, memory protection, virtual memory, paging, segmentation, cache hierarchy, write-back cache, write-through cache, no-write-allocate cache, cache coherence protocol, bus architecture, address bus, data bus, control bus, clock signal, power management, sleep mode, idle mode.